ASML’s grip on the most advanced corner of chip manufacturing is tightening. The Dutch company, already the sole supplier of extreme ultraviolet lithography systems, is winning broader industry support for High Numerical Aperture EUV, or High NA, its next-generation technology for printing smaller and denser circuitry.
That support matters because High NA machines cost roughly $400 million each, about twice as much as conventional EUV systems. Their adoption therefore depends on more than technical performance: chipmakers must believe the tools can improve yields, reduce production steps and remain useful across several generations of processors. Recent commitments from Intel, Samsung, TSMC and SK Hynix indicate that the industry is increasingly convinced.
High NA raises the numerical aperture of the optical system from 0.33 to 0.55, enabling features about 40% smaller than those produced by current EUV tools. That higher resolution can replace multiple patterning steps with a single exposure, simplifying manufacturing and potentially reducing defects. It also helps chipmakers continue transistor scaling as older techniques become increasingly complicated and expensive.
Intel has taken the early lead. In July, ASML said Intel Foundry had begun using High NA on selected layers of its 18A process for Panther Lake processors, making it the first company to ship a high-volume logic product made with the technology. The selected layers achieved yields matching Intel’s established NXE platform, giving ASML an important real-world validation beyond laboratory demonstrations. Intel has since processed more than one million wafers with High NA systems, including research, qualification and production runs.
Other major customers are now outlining timelines. Samsung plans to introduce High NA into high-volume DRAM manufacturing by 2028, while SK Hynix is also targeting memory production around that period. TSMC, which had questioned whether the technology’s cost justified early adoption, now expects to deploy it by 2030. These schedules vary, but collectively they reduce the risk that High NA becomes a niche tool tied mainly to Intel’s roadmap.
The shift reinforces a formidable competitive position. ASML held about 94% of the lithography market in 2025 and has no commercial rival in EUV. Nikon and Canon remain active in older lithography categories, while Chinese suppliers are working to close the technology gap. Yet replicating ASML’s ecosystem of precision optics, powerful light sources, software and thousands of specialized components would require enormous capital and years of coordinated development.
High NA is not free of compromises. Its anamorphic optics expose only half the field size of existing EUV systems, creating difficulties for very large AI accelerators and data-center chips. Manufacturers may need to divide designs and stitch the exposures together, adding complexity and potential yield risk. ASML is working with Intel, Samsung, TSMC and other partners on a larger photomask platform that would restore full-field capability. A pilot line is planned for 2031, followed by high-volume readiness in 2033.
Capacity is another challenge. Demand generated by AI investment has nearly filled ASML’s conventional EUV production slots through 2027. The company is examining how to build more than 110 EUV machines in 2028, up from at least 80 expected in 2027, while also expanding manufacturing facilities near its Veldhoven headquarters. Scaling depends on suppliers such as optics specialist Carl Zeiss as much as on ASML itself.
The economics could strengthen further as the EXE platform matures. ASML says its newer EXE:5200B can process 175 wafers an hour, 60% more than the earlier EXE:5000. Higher throughput spreads the machine’s purchase price across more chips and improves its appeal to cautious customers.
Bottom line: For customers, committing early secures access and influence over a technology likely to shape manufacturing in the 2030s. For ASML, every adoption decision deepens its installed base, service revenue and strategic importance. High NA may initially contribute modest shipment volumes, but its broader significance is clear: the semiconductor industry is again organizing its next leap in miniaturization around machinery that only ASML can provide.
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Facts Only
* ASML is the sole supplier of extreme ultraviolet lithography systems.
* High NA is the next-generation technology for printing smaller and denser circuitry.
* High NA machines cost approximately $400 million each, about twice as much as conventional EUV systems.
* High NA raises the numerical aperture from 0.33 to 0.55.
* High NA enables features about 40% smaller than those produced by current EUV tools.
* High NA allows replacing multiple patterning steps with a single exposure.
* Intel Foundry began using High NA on selected layers of its 18A process for Panther Lake processors in July.
* Intel has processed over one million wafers with High NA systems, including research, qualification, and production runs.
* Samsung plans to introduce High NA into high-volume DRAM manufacturing by 2028.
* SK Hynix is targeting memory production around 2028.
* TSMC expects to deploy High NA by 2030.
* ASML is working with partners on a larger photomask platform for full-field capability, planned for a pilot line in 2031 and high-volume readiness in 2033.
* Demand generated by AI investment nearly filled ASML’s conventional EUV production slots through 2027.
Executive Summary
ASML, the sole supplier of extreme ultraviolet lithography systems, is gaining broader industry support for High Numerical Aperture EUV (High NA), a next-generation technology for printing denser circuitry. This shift is driven by the high cost of High NA machines, which are approximately twice the price of conventional EUV systems, necessitating that chipmakers see benefits in yield improvement, reduced production steps, and multi-generational utility. Major customers, including Intel, Samsung, TSMC, and SK Hynix, have signaled increasing conviction.
The technical advantage of High NA is raising the numerical aperture from 0.33 to 0.55, allowing features approximately 40% smaller than current EUV capabilities, which can consolidate multiple patterning steps into a single exposure. This advancement supports continued transistor scaling and defect reduction. While initial adoption faced cost barriers, timelines are emerging: Samsung plans High NA for DRAM by 2028, SK Hynix targets memory production around the same time, and TSMC expects deployment by 2030.
Despite this industry shift, High NA presents technical compromises, as its anamorphic optics expose only half the field size of existing EUV tools, potentially complicating designs for large AI accelerators. ASML is actively mitigating these limitations by developing a larger photomask platform to restore full-field capability. Capacity expansion is also a concern, with demand nearing conventional EUV slots; ASML is planning to increase EUV machine production and expanding facilities.
Full Take
The narrative pivots on the tension between technological capability, economic reality, and supply chain centralization. The industry is moving toward High NA not simply for performance gains, but as a necessary evolution to sustain miniaturization against compounding complexity, suggesting that technical constraint is now an economic driver. The initial reluctance surrounding the cost of High NA is being overcome by demonstrated validation from key foundry customers, shifting the focus from pure R&D promises to demonstrable production readiness across multiple entities.
The pattern observed here is one of inevitable technological convergence driven by competitive necessity. ASML’s unique position provides a structural advantage, which is difficult to replicate given the immense capital and coordination required to build an equivalent ecosystem. The challenge shifts from whether High NA *can* be achieved to how the industry will manage the necessary trade-offs—specifically the compromise in field size—and scale the infrastructure. The planned work on the larger photomask platform suggests a strategic maneuver: addressing the technical limitations by leveraging ASML's dominance, which is a classic mechanism for maintaining control over a crucial bottleneck.
The unstated implication is that future semiconductor manufacturing will be defined less by incremental performance gains and more by the ability to secure comprehensive, coordinated infrastructure capable of handling radical physical shifts. The risk lies in whether the pursuit of broader adoption and larger tooling ultimately mandates compromises that slow down the theoretical benefits of higher resolution, or if the commitment to scale will force innovation around mitigating those initial limitations through cooperative platform development.